With development of display technology, display panels having high transmittance, large size, low energy consumption and low cost have become a developing tendency in future.
Most gate scanning lines in array substrates of TFT-LCD have a single-line structure. FIG. 1 is a top view illustrating a structure of an array substrate, and FIG. 2 is a sectional view taken along line A-A in FIG. 2. As shown in FIG. 1 and FIG. 2, a gate scanning line 12 is formed on a glass substrate 11, and an insulating layer 13 is covered on the gate scanning line 12; the insulating layer 13 is usually consisted of silicon nitride. An active layer 14 is formed on the insulating layer 13, and a data scanning line 15 is formed on the active layer 14; the data scanning line 15 is etched to form a source electrode and a drain electrode of a thin film transistor (TFT). A protective layer 16 is formed on the data scanning line 15 and is etched to form a via-hole above the drain electrode of the TFT. Then a pixel electrode 17 is formed on the protective layer and connected to the drain electrode of the TFT through the via-hole in the protective layer 16.
In order to reduce the number of data drivers as used so as to lower the cost, another structure of duel-gate scanning line is proposed. In such structure of duel-gate scanning line, two gate scanning lines are arranged in parallel on a same layer; although the number of scanning lines is doubled, the total number of data drivers as required is still reduced because the number of data lines is halved.